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Effect of glitches against masked AES S-box implementation and countermeasure

机译：毛刺对掩模aEs s盒实施的影响及对策

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M. Alam; S. Ghosh; M. J. Mohan; D. Mukhopadhyay;
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年度 2008
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1. An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm [J] . Ye Yunfei, Wu Ning, Zhang Xiaoqiang, Journal of circuits, systems and computers . 2018,第11期

机译：基于复合场和通用子表达式消除算法的紧凑型带遮罩的AES S盒优化设计
2. Parallel AES Encryption Engine for Many Core Processor Arrays Using Masked S-Box [J] . Dhanya Pushkaran, Neethu Bhaskar International Journal of Recent Contributions from Engineering, Science & IT . 2014,第4期

机译：使用蒙版S-Box的许多核心处理器阵列的并行AES加密引擎
3. FPGA Based Implementation of AES Encryption and Decryption with Low Power Multiplexer LUT Based S-Box [J] . Ratheesh T, Seena Narayanan IOSR Journal of Electronics and Communication Engineering . 2017,第2期

机译：基于FPGA的低功耗多路复用器LUT基于S-Box的AES加密和解密实现
4. SRAM-FPGA implementation of masked S-Box based DPA countermeasure for AES [C] . Kamoun Najeh, Bossuet Lilian, Ghazel Adel International Design Test Workshop . 2008

机译：SRAM-FPGA基于蒙版的AES的DPA对策
5. Area efficient implementation of the advanced encryption standard S-BOX logic functions [D] . Uang, Jia Bao. 2009

机译：区域高效实现高级加密标准S型盒逻辑功能
6. Design of cryptographically secure AES like S-Box using second-order reversible cellular automata for wireless body area network applications [O] . Bhoopal Rao Gangadari, Shaik Rafi Ahamed 2016

机译：使用二阶可逆蜂窝自动机设计用于S-Box的加密安全AES用于无线人体局域网应用
7. Parallel AES Encryption Engine for Many Core Processor Arrays Using Masked S-Box [O] . Dhanya Pushkaran, Neethu Bhaskar 2014

机译：使用屏蔽S框的许多核心处理器阵列的并行AES加密引擎

Effect of glitches against masked AES S-box implementation and countermeasure

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