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Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors

机译：数字信号处理器中VLIW指令集架构的动态码宽减少

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Matthias Weiss; Gerhard P. Fettweis;
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年度 1996
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1. Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture [J] . Cheng-Yu Lee, Min-Chin Hung, Rong-Guey Chang Concurrency and computation: practice and experience . 2014,第1期

机译：具有共享寄存器架构的VLIW统一精简指令集计算机/数字信号处理器处理器的指令调度和转换
2. Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project [J] . Jordans Roel, Jozwiak Lech, Corporaal Henk, Microprocessors and microsystems . 2017,第juna期

机译：ASAM项目中VLIW处理器内核的自动指令集架构综合
3. A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors [J] . Shu Xiao, Lai E.M.-K. IEEE Transactions on Signal Processing . 2008,第4期

机译：VLIW数字信号处理器的功率平衡指令调度的粗糙编程方法
4. Dynamic Codwidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors [C] . Matthias H. Weiss, Gerhard P. Fettweis 3rd International Workshop on Image/Signal Processing (IWISP): Advances in Computational Intelligent 4-7 November, 1996 UMIST, Manchester, UK . 1996

机译：数字信号处理器中VLIW指令集架构的动态Codwidth降低
5. Computational limits of VLIW architectures for digital signal processing transforms. [D] . Sankaran, Jagadeesh. 2003

机译：用于数字信号处理转换的VLIW架构的计算限制。
6. Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures [O] . Haijing Tang, Xu Yang, Siye Wang, 2013

机译：连接寄存器文件的集群式VLIW架构的优化指令调度和寄存器分配
7. A Hybrid Hardware/Software Architecture That Combines a 4-wide Very Long Instruction Word Software Processor (VLIW) with Application-specific Super-complex Instruction Set Hardware Functions [O] . Kusic Dara Marie 2005

机译：混合硬件/软件体系结构，将4宽超长指令字软件处理器（VLIW）与特定于应用程序的超复杂指令集硬件功能相结合
8. Application of Compiler-Assisted Multiple Instruction Retry to VLIW Architectures [R] . Chen, S. K., Fuchs, W. K., Hwu, W. M. W. 1994

机译：编译辅助多指令重试在VLIW体系结构中的应用

Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors

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