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DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures

机译：DREsC：用于粗粒度可重构体系结构的可重定向编译器

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Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins; Bingfeng Mei Ýþ; Serge Vernalde Ý; Diederik Verkest Ý; Hugo De; Man Ýþ; Rudy Lauwereins Ýþ;
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年度 2002
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1. A Retargetable Compiler Based On Graph Representation For Dynamically Reconfigurable Processor Arrays [J] . Vasutan TUNBUNHENG, Hideharu AMANO IEICE Transactions on Information and Systems . 2008,第11期

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2. Inter-coarse-grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel-stream on coarse-grained reconfigurable architecture-based multi-core architecture [J] . Yoonjin Kim, Hyejin Joo, Sohyun Yoon Circuits, Devices & Systems, IET . 2016,第4期

机译：粗粒度间可重配置体系结构重配置技术，可在基于粗粒度可重配置体系结构的多核体系结构上有效地流化内核流
3. A retargetable framework for compiler/architecture co-development [J] . Hanno Scharwaechter, David Kammler, Rainer Leupers, Design automation for embedded systems . 2011,第3a4期

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4. DRESC: a retargetable compiler for coarse-grained reconfigurable architectures [C] . Bingfeng Mei, Vernalde S., Verkest D., Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on . 2002

机译：DRESC：用于粗粒度可重配置架构的可重定位编译器
5. A retargetable compiler and virtual machine based methodology for assessment of instruction set architectures. [D] . Stepanian, Robert. 1992

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6. Design and Benchmark Testing for Open Architecture Reconfigurable Mobile Spirometer and Exhaled Breath Monitor with GPS and Data Telemetry [O] . Alexander G. Fung, Laren D. Tan, Theresa N. Duong, 2019

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7. Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures [O] . Grigoris Dimitroulakos, See Profile, Gregory Dimitroulakos, 2016

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DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures

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