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Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits

机译：内置一代同步时序电路的加权测试序列

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Irith Pomeranz And;
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年度 2000
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1. Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits [J] . Pomeranz I., Reddy S.M. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2006,第6期

机译：透明DFT：针对同步时序电路的可测试性和测试生成方法的设计
2. Primary input cones based on test sequences in synchronous sequential circuits [J] . Pomeranz I., Reddy S.M. Computers & Digital Techniques, IET . 2011,第1期

机译：基于同步时序电路中测试序列的主输入锥
3. Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits [J] . Pomeranz I., Reddy S. M. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2008,第1期

机译：同步时序电路的随机测试序列中应避免的主要输入向量
4. Built-in generation of weighted test sequences for synchronous sequential circuits [C] . Irith Pomeranz, Sudhakar M. Reddy, PIrith Pomeranz, Annual Workshop on Petascale Data Storage;Workshop on Petascale Data Storage . 2009

机译：内置生成同步时序电路的加权测试序列
5. AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS, [D] . BELT, JOHN EDWARD. 1973

机译：一种针对AHPL（硬件编程语言）描述的同步顺序电路的测试序列生成的启发式搜索方法，
6. Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits [O] . Minhyun Jin, Hyeonseob Noh, Minkyu Song, 2020

机译：具有内置掩模电路的边缘检测CMOS图像传感器的设计
7. Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits+ [O] . Sudhakar Reddy, See Profile, Irith Pomeranz, 2000

机译：内置生成的同步时序电路加权测试序列+
8. Automatic Test Pattern Generation for Synchronous Sequential Circuits [R] . Konijnenburg, M. H. 1998

机译：同步时序电路的自动测试模式生成

Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits

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