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Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits

机译：有效识别同步时序电路中无法区分的故障对的定理

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M. Enamul Amyeen; Irith Pomeranz; W. Kent Fuchs;
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年度 2007
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专利

1. HOPE: an efficient parallel fault simulator for synchronous sequential circuits [J] . Hyung Ki Lee, Dong Sam Ha IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1996,第9期

机译：HOPE：用于同步时序电路的高效并行故障模拟器
2. Combinational ATPG theorems for identifying untestable faults in sequential circuits [J] . Agrawal V.D., Chakradhar S.T. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1995,第9期

机译：组合式ATPG定理，用于确定顺序电路中无法测试的故障
3. Double–Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits [J] . Pomeranz I., Reddy S. M. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2009,第3期

机译：双卡住故障：同步时序电路的延迟故障模型
4. Theorems for efficient identification of indistinguishable fault pairs in synchronous sequential circuits [C] . Amyeen, M.E., Pomeranz, . 2002

机译：有效识别同步时序电路中无法区分的故障对的定理
5. An efficient test-pattern relaxation technique for synchronous sequential circuits. [D] . Al-Utaibi, Khaled Abdul-Aziz. 2002

机译：一种用于同步时序电路的有效测试模式松弛技术。
6. A pair-rule gene circuit defines segments sequentially in the short-germ insect Tribolium castaneum [O] . Chong Pyo Choe, Sherry C. Miller, Susan J. Brown 2006

机译：一个成对规则的基因电路按顺序定义了短种昆虫Tribolium castaneum中的片段
7. Efficient Calculation of All-Pairs Input-to-Output Delays in Synchronous Sequential Circuits [O] . Sachin S. Sapatnekar 2007

机译：同步时序电路中全对输入到输出延迟的有效计算
8. Analysis of Multiple Faults in Synchronous Sequential Circuits by Boolean Difference Techniques [R] . Goldstein, L. H. 1978

机译：用布尔差分技术分析同步时序电路中的多个故障

Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits

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