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A Practical Approach to Parasitic Extraction for Design of Multimillion-Transistor Integrated Circuits

机译：数百万集成电路设计中寄生提取的实用方法

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Eileen You; Lakshminarasimh Varadadesikan; John Macdonald; Wieze Xie;
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年度 2013
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1. Neural-Network-Based Parasitic Modeling and Extraction Verification for RF/Millimeter-Wave Integrated Circuit Design [J] . Padmanava Sen, Wayne H. Woods, Saikat Sarkar, IEEE Transactions on Microwave Theory and Techniques . 2006,第6期

机译：RF /毫米波集成电路设计的基于神经网络的寄生建模和提取验证
2. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods [J] . Ren Dan, Xu Xiaoyu, Qu Hui, Journal of Semiconductors . 2015,第4期

机译：用双重离散几何方法提取集成电路的二维寄生电容
3. Getting the balance right - some practical design considerations for solvent extraction circuits [J] . G. Laing Journal Of The South African Institute Of Mining & Metallurgy . 2002,第8期

机译：取得平衡-溶剂萃取回路的一些实际设计考虑
4. A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits [C] . Eileen You, Lakshminarasimh Varadadesikan, John MacDonald, Conference on Design automation . 2000

机译：数百万晶体管集成电路设计中寄生提取的实用方法
5. Layout extraction including substrate parasitics for ESD protection circuits and design rule checking. [D] . Li, Qiao. 2001

机译：布局提取包括用于ESD保护电路和设计规则检查的基板寄生物。
6. Rigorous Approach for Design of Differential Coupled-Line Directional Couplers Applicable in Integrated Circuits and Substrate-Embedded Networks [O] . Kamil Staszek, Krzysztof Wincza, Slawomir Gruszczynski -1

机译：设计适用于集成电路和衬底嵌入式网络的差分耦合线定向耦合器的严格方法
7. Efficient Design-Specific Worst-Case Corner Extraction for Integrated Circuits [O] . Hong Zhang, Tsung-Hao Chen, Ming-Yuan Ting, 2009

机译：针对集成电路的高效设计特定的最坏情况角点提取
8. Extraction of MOS VLSI (Very-Large-Scale-Integrated) Circuit Models Including Critical Interconnect Parasitics [R] . Su, S. L. 1987

机译：提取包括关键互连寄生效应的mOs VLsI（超大规模集成）电路模型

A Practical Approach to Parasitic Extraction for Design of Multimillion-Transistor Integrated Circuits

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