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Dual-vdd interconnect with chip-level time slack allocation for FPGA power reduction

机译：具有芯片级时间余量分配的双vdd互连，可降低FPGA功耗

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Yan Lin; Lei He;
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年度 2006
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1. Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction [J] . Lin Y., He L. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2006,第10期

机译：具有芯片级时间松弛分配的双Vdd互连，可降低FPGA功耗
2. Physical Synthesis for FPGA Interconnect Power Reduction by Dual-Vdd Budgeting and Retiming [J] . YU HU, YAN LIN, LEI HE, ACM Transactions on Design Automation of Electronic Systems . 2008,第2期

机译：通过双Vdd预算和重新定时降低FPGA互连功耗的物理综合
3. Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power One-Time-Programmable (OTP) FPGA Interconnects [J] . He Tina, Zhang Fengchao, Bhunia Swarup, Electron Devices Society, IEE . 2015,第4期

机译：用于超低功耗一次性可编程（OTP）FPGA互连的碳化硅（SiC）纳米机电反熔丝
4. An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction [C] . Yan Lin, Yu Hu, Lei He, International symposium on Low power electronics and design . 2006

机译：一种有效的芯片级时间松弛分配算法，可降低Dual-Vdd FPGA的功耗
5. Low-Swing Signaling for FPGA Interconnect Power Reduction. [D] . Sharifymoghaddam, Sayeh. 2015

机译：用于FPGA互连功耗降低的低摆信号。
6. Single-chip photonic transceiver based on bulk-silicon as a chip-level photonic I/O platform for optical interconnects [O] . Gyungock Kim, Hyundai Park, Jiho Joo, -1

机译：基于体硅的单芯片光子收发器作为用于光学互连的芯片级光子I / O平台
7. An Efficient Chip-level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction ∗ [O] . 2008

机译：用于双Vdd FpGa功率降低的高效芯片级时隙分配算法*

Dual-vdd interconnect with chip-level time slack allocation for FPGA power reduction

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