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A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

机译：具有差动读取能力的软容错10T SRAM位单元

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Shah M. Jahinuzzaman; David J. Rennie; Manoj Sachdev; Senior Member;
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年度 2013
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1. Bias Temperature Instability Aware and Soft Error Tolerant Radiation Hardened 10T SRAM Cell [J] . Progress in Artificial Intelligence . 2020,第2期

机译：偏置温度不稳定性意识到和软误差耐受辐射硬化10T SRAM单元
2. Pentavariate$V_{mathrm{min}}$Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read [J] . Shourya Gupta, Kirti Gupta, Neeta Pandey IEEE transactions on circuits and systems . I , Regular papers . 2018,第10期

机译：Pentavariate $ V_ {mathrm {min}} $ 具有可变容差的亚阈值10T SRAM位单元的分析和分位线读取
3. Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications [J] . Pooran Singh, Santosh Kumar Vishvakarma Journal of Low Power Electronics and Applications . 2017,第3期

机译：超低功耗，过程耐受性10T（PT10T）SRAM，具有改进的物联网（IoT）应用读写能力
4. A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS [C] . Ik Joon Chang, Jae-Joon Kim, Park S.P., IEEE International Solid-State Circuits Conference . 2008

机译：具有90nm CMOS中的32KB 10T亚阈值SRAM阵列，位交错和差分读取方案
5. Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error resilience and performance. [D] . Cha, Jae Chul. 2010

机译：在软错误恢复能力和性能约束下，根据每单位面积产量的最佳容错SRAM设计。
6. A Soft-Error-Tolerant SAR ADC with Dual-Capacitor Sample-and-Hold Control for Sensor Systems [O] . Duckhoon Ro, Minseong Um, Hyung-Min Lee 2021

机译：具有双电容器样品和保持控制的软堵塞SAR ADC用于传感器系统
7. Bias Temperature Instability Aware and Soft Error Tolerant Radiation Hardened 10T SRAM Cell [O] . Ambika Prasad Shah, Michael Waltl 2020

机译：偏置温度不稳定性意识到和软误差耐受辐射硬化10T SRAM单元

A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

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