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Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures

机译：快速的周期精确仿真和指令集生成，用于基于约束的可编程体系结构描述

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Scott J. Weber; Matthew W. Moskewicz; Matthias Gries; Christian Sauer; Kurt Keutzer;
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年度 2004
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1. Architecture Description Language (ADL)-Driven Software Toolkit Generation for Architectural Exploration of Programmable SOCs [J] . PRABHAT MISHRA, AVIRAL SHRIVASTAVA, NIKIL DUTT ACM Transactions on Design Automation of Electronic Systems . 2006,第3期

机译：架构描述语言（ADL）驱动的软件工具包生成，用于可编程SOC的架构探索
2. Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator [J] . HOONMO YANG, MOONKEY LEE Journal of supercomputing . 2005,第1a2期

机译：使用周期精确的可重定向指令集模拟器的嵌入式处理器验证环境
3. A Parameterized Programmable MIMO Decoding Architecture With a Scalable Instruction Set and Compiler [J] . Mohammed K., Mohamed M. I. A., Daneshrad B. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2011,第8期

机译：具有可扩展指令集和编译器的参数化可编程MIMO解码架构
4. Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures [C] . Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis . 2004

机译：快速的周期精确仿真和指令集生成，用于基于约束的可编程体系结构描述
5. Virtualize or Keep It Real? a Study of GPU Instruction Set Architectures and Their Effects in Simulations [D] . Jain, Akshay. 2017

机译：虚拟化或保持真实吗？ GPU指令集架构的研究及其在模拟中的影响
6. NeuroLab: A Set of Graphical Computer Simulations to Support Neuroscience Instruction at the High School and Undergraduate Level [O] . Luis F. Schettino 2014

机译：NeuroLab：一组图形计算机模拟可支持高中和本科阶段的神经科学教学
7. Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution [O] . Buchty Rainer 2006

机译：可重构架构和指令集：可编程性，代码生成和程序执行
8. EVALUATION OF INSTRUCTION SET PROCESSOR ARCHITECTURE BY PROGRAM TRACING [R] . Amund Lunde 1974

机译：用程序跟踪评估指令集处理器体系结构

Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures

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