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Interconnect Scaling: Signal Integrity and Performance in Future High-Speed CMOS Designs

机译：互连缩放：未来高速CMOS设计中的信号完整性和性能

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Dennis Sylvester Chenming; Dennis Sylvester; Chenming Hu; O. Sam Nakagawa; Soo-young Oh;
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年度 1998
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1. Scalable Model of On-Wafer Interconnects for High-Speed CMOS ICs [J] . Xiaomeng Shi, Kiat Seng Yeo, Jian-Guo Ma, IEEE Transactions on Advanced Packaging . 2006,第期

机译：高速CMOS IC的晶圆上互连的可扩展模型
2. Scalable Model of On-Wafer Interconnects for High-Speed CMOS ICs [J] . Xiaomeng Shi, Kiat Seng Yeo, Jian-Guo Ma, IEEE Transactions on Advanced Packaging . 2006,第4期

机译：高速CMOS IC的晶圆上互连的可扩展模型
3. CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects [J] . Jose C. Garcia, Juan A. Montiei-Nelson, Saeid Nooshabadi Microelectronics journal . 2009,第11期

机译：用于节能片上互连的CMOS设计和低压信令方法分析
4. Interconnect scaling: signal integrity and performance in future high-speed CMOS designs [C] . Sylvester, D., Chenming Hu . 1998

机译：互连缩放：未来高速CMOS设计中的信号完整性和性能
5. Cost-effective interconnect and circuit design methods for high-speed nanometer CMOS VLSI design. [D] . Akl, Charbel J. 2008

机译：用于高速纳米CMOS VLSI设计的经济高效的互连和电路设计方法。
6. Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications [O] . Bilal I. Abdulrazzaq, Omar J. Ibrahim, Shoji Kawahito, 2016

机译：具有可调范围CMOS延迟锁定环路的亚皮秒抖动设计适用于高速和低功耗应用
7. DESIGN AND SIMULATION OF CMOS CIRCUIT STRUCTURE FOR CTL-CTM CROSSTALK CANCELLATION METHOD IN HIGH-SPEED INTERCONNECTS [O] . Huifang Sun, Yafei Wang, Yanxiao Zhao, 2021

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Interconnect Scaling: Signal Integrity and Performance in Future High-Speed CMOS Designs

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