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Gate-level design exploiting dual supply voltages for power-driven applications

机译：在电源驱动应用中利用双电源电压进行门级设计

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Chingwei Yeh; Min-cheng Chang; Shih-chieh Chang; Wen-bone Jone;
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年度 1999
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1. Gate-level voltage scaling for low-power design using multiple supply voltages [J] . Yeh C., Chang M.-C. IEE proceedings. Part G . 1999,第6期

机译：使用多个电源电压进行低功耗设计的门级电压缩放
2. Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages [J] . Diril A.U., Dhillon Y.S., Chatterjee A., IEEE transactions on very large scale integration (VLSI) systems . 2005,第9期

机译：使用双阈值电压的低功率双电源电压CMOS电路的无电平转换器设计
3. Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy [J] . Jung Dongha, Lee Hokyoon, Kim Seon Wook ACM Transactions on Design Automation of Electronic Systems . 2016,第1期

机译：通过利用数据冗余降低用于节能缓存设计的最小电源电压
4. Gate-level design exploiting dual supply voltages for power-driven applications [C] . Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, ACM/IEEE conference on Design automation . 1999

机译：门级设计，利用双电源电压驱动电源应用
5. Design and Control of Power Converters for Medium Voltage DC Applications Enabled by Medium Voltage SiC-MOSFETs [D] . Acharya, Sayan. 2019

机译：中电压SiC-MOSFET启用的中电压DC应用的功率转换器的设计与控制
6. A novel power-driven fractional accumulated grey model and its application in forecasting wind energy consumption of China [O] . Peng Zhang, Xin Ma, Kun She 2019

机译：一种新型动力驱动的分数累计灰色模型及其在预测中国风能消费中的应用
7. Gate-level design exploiting dual supply voltages for power-driven applications [O] . YehChingwei, ChangMin-Cheng, ChangShih-Chieh, 1999

机译：在电源驱动应用中采用双电源电压的门级设计

Gate-level design exploiting dual supply voltages for power-driven applications

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