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Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

机译：基于ECC的100nm以下SRAM硬化方法的模型和算法限制

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Michael A. Bajura; Younes Boulghassoul; Riaz Naseer; Student Member; Eepan Dasgupta; Arthur F. Witulski; Senior Member; Jeff Sondeen; Scott D. Stansberry; Jeffrey Draper; Lloyd W. Massengill; John N. Damoulakis;
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1. Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias [J] . Mukhopadhyay S., Mahmoodi H., Roy K. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2008,第1期

机译：使用体偏置减少100 nm以下SRAM阵列中的参数故障
2. Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation [J] . Hyunwoo Nho, Sei-Seung Yoon, Wong S.S., IEEE transactions on circuits and systems. II, Express briefs . 2008,第9期

机译：使用蒙特卡洛模拟的100nm以下SRAM设计产量的数值估算
3. AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement [J] . Ihsen Alouani, Wael M. Elsharkasy, Ahmed M. Eltawil, Circuits, Devices & Systems, IET . 2017,第1期

机译：AS8静态随机存取存储器（SRAM）：非对称SRAM架构，用于软错误强化增强
4. A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design [C] . Yamaoka, M., Onodera, SOC Conference, 2006 IEEE International . 2006

机译：100nm以下嵌入式SRAM设计的详细Vth变异分析
5. Analysis and Modeling of Large-Scale Variation on DACs and SRAMs. [D] . Park, Henry Arnold. 2013

机译：DAC和SRAM上大规模变化的分析和建模。
6. New Approach for Risk Estimation Algorithms of BRCA1/2 Negativeness Detection with Modelling Supervised Machine Learning Techniques [O] . Hulya Yazici, Demet Akdeniz Odemis, Dogukan Aksu, 2020

机译：BRCA1 / 2消极检测风险估计算法的新方法采用造型监督机学习技术
7. SRAM delay fault modeling and test algorithm development [O] . Rei-fu Huang, Yan-ting Lai, Yung-fa Chou, 2004

机译：sRam延迟故障建模和测试算法开发
8. Single Event Effects on Space Radiation Hardened 64K SRAMS at Room temperature [R] . Kim, O., Schwartz, H., McCarty, K., 1993

机译：室温下单粒子对空间辐射强化64K sRams的影响

Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

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