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Concurrent Flip-Flop and Repeater Insertion for High Performance Integrated Circuits

机译：高性能集成电路的并发触发器和中继器插入

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1. The BOOM Project: Towards 160 Gb/s Packet Switching Using SOI Photonic Integrated Circuits and Hybrid Integrated Optical Flip-Flops [J] . Stamatiadis C., Gomez-Agis F., Stampoulidis L., Lightwave Technology, Journal of . 2012,第1期

机译：BOOM项目：使用SOI光子集成电路和混合集成光触发器实现160 Gb / s分组交换
2. Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits [J] . Ku J. C., Ismail Y. IEEE transactions on very large scale integration (VLSI) systems . 2007,第8期

机译：低功率VLSI电路中中继器插入的热感知方法
3. Repeater insertion in global interconnects in VLSI circuits [J] . Rajeevan Chandel, S. Sarkar, R. P. Agarwal Microelectronics international: Journal of ISHM--Europe, the Microelectronics Society--Europe . 2005,第1期

机译：在VLSI电路的全局互连中插入中继器
4. Concurrent flip-flop and repeater insertion for high performance integrated circuits [C] . Cocchini, P. . 2002

机译：并发触发器和中继器插入，用于高性能集成电路
5. Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability [D] . Ausoori, Raghuveer 2009

机译：测试点，部分扫描和全扫描触发器插入的信息理论和频谱方法，以提高集成电路的可测试性
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7. Concurrent flip-flop and repeater insertion for high performance integrated circuits [O] . Pasquale Cocchini 2015

机译：用于高性能集成电路的并发触发器和中继器插入
8. Clock Tree Insertion and Verification for 3D Integrated Circuits [R] . Mineo, C. A. 2005

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Concurrent Flip-Flop and Repeater Insertion for High Performance Integrated Circuits

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