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Simulation of Lithography-caused Gate Length and Interconnect Linewidth Variational Impact on Circuit Performance in Nanoscale Semiconductor Manufacturing

机译：光刻引起的栅极长度和互连线宽变化对纳米级半导体制造中电路性能的影响的仿真

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Munkang Choi; Cheng Jia; Linda Milor;
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年度 2009
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1. Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing [J] . Munkang Choi, Milor L. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2006,第7期

机译：纳米级半导体制造中确定性晶粒内变异对电路性能的影响
2. Selection of gate length and gate bias to make nanoscale metal-oxide-semiconductor transistors less sensitive to both statistical gate length variation and temperature variation [J] . Peizhen Yang, W.S. Lau, Seow Wei Lai, Solid-State Electronics . 2010,第11期

机译：选择栅极长度和栅极偏置，以使纳米级金属氧化物半导体晶体管对统计的栅极长度变化和温度变化均不敏感
3. Analysis of DC Characteristics and Small Signal Equivalent Circuit Parameters of GaAs Metal-Semiconductor Field Effect Transistors with Different Gate Lengths and Different Gate Contours by Two-Dimensional Device Simulations [J] . C. C. MENG, J. Y. SU, S. M. YANG Japanese Journal of Applied Physics. Part 1, Regular Papers, Brief Communications & Review Papers . 2005,第9A期

机译：二维器件仿真分析不同栅长和栅轮廓的砷化镓金属半导体场效应晶体管的直流特性和小信号等效电路参数
4. Simulation of Lithography-caused Gate Length and Interconnect Linewidth Variational Impact on Circuit Performance in Nanoscale Semiconductor Manufacturing [C] . Munkang Choi, Cheng Jia, Linda Milor International Conference on Simulation of Semiconductor Processes and Devices(SISPAD 2004); 20040902-04; Munich(DE) . 2004

机译：光刻引起的栅极长度和互连线宽变化对纳米级半导体制造中电路性能的影响的仿真
5. Modeling the effects of device and interconnect process variation on high-speed circuit performance. [D] . Khazamipour, Ali Asghar. 2003

机译：建模器件和互连工艺变化对高速电路性能的影响。
6. Lengths of the C-Terminus and Interconnecting Loops Impact Stability of Spider-Derived Gating Modifier Toxins [O] . Akello J. Agwa, Yen-Hua Huang, David J. Craik, 2017

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7. Geometric linewidth and the impact of thermal processing on the stress regimes induced by electroless copper metallization for Si integrated circuit interconnect technology [O] . McNally, P.J., Kanatharana, J., Toh, B.H.W., 2004

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8. Long-Wavelength Vertical Cavity Lasers with Air/Semiconductor Mirrors: Nanoscale Gate Technology for Silicon MOSFETS [R] . Bokor, J. , Lindert, N. 2000

机译：具有空气/半导体反射镜的长波长垂直腔体激光器：用于硅mOsFET的纳米级栅极技术

Simulation of Lithography-caused Gate Length and Interconnect Linewidth Variational Impact on Circuit Performance in Nanoscale Semiconductor Manufacturing

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