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Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures

机译：用于在水平分区的高速缓存体系结构中减少能耗的在环编译器设计空间探索框架

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Aviral Shrivastava; Ilya Issenin; Nikil Dutt; Sanghyun Park; Yunheung Paek;
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年度 2012
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1. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures [J] . Shrivastava A., Issenin I., Dutt N., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2009,第3期

机译：用于在水平分区的缓存体系结构中减少能耗的在环编译器设计空间探索框架
2. Fine-grained and coarse-grained behavioral partitioning witheffective utilization of memory and design space exploration formulti-FPGA architectures [J] . Srinivasan V., Govindarajan S., Vemuri R. IEEE transactions on very large scale integration (VLSI) systems . 2001,第1期

机译：细粒度和粗粒度行为分区，有效利用内存，并探索多FPGA架构的设计空间
3. Grey Wolf Optimizer Driven design space exploration: A novel framework for multi-objective trade-off in architectural synthesis [J] . Siddavaatam Prathap, Sedaghat Reza Swarm and Evolutionary Computation . 2019,第期

机译：灰狼优化器驱动设计空间探索：建筑综合的多目标权衡的新框架
4. A compiler-in-the-loop framework to explore horizontally partitioned cache architectures [C] . Aviral Shrivastava, Ilya Issenin, Nikil Dutt Proceedings of the 2008 conference on Asia and South Pacific design automation . 2008

机译：循环编译器框架，用于探索水平分区的缓存体系结构
5. An efficient design space exploration framework to optimize power-efficient heterogeneous many-core multi-threading embedded processor architectures. [D] . Datta, Kushal. 2011

机译：一个有效的设计空间探索框架，用于优化省电的异构多核多线程嵌入式处理器体系结构。
6. Exploration of a Capability-Focused Aerospace System of Systems Architecture Alternative with Bilayer Design Space Based on RST-SOM Algorithmic Methods [O] . Zhifei Li, Dongliang Qin, Feng Yang -1

机译：基于RST-SOM算法的以双层设计空间为中心的以系统架构替代能力为重点的航空航天系统的探索
7. A Compiler-in-the-Loop Framework to Explore Horizontally Partitioned Cache Architectures [O] . Aviral Shrivastava, Ilya Issenin, Nikil Dutt 2008

机译：用于探索水平分区缓存架构的编译器在环框架

Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures

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