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Noise Estimation Due To Signal Activity For Capacitively Coupled CMOS Logic Gates

机译：电容耦合的CMOS逻辑门的信号活动引起的噪声估计

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Kevin T. Tang; Eby G. Friedman;
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年度 2000
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1. Delay and noise estimation of CMOS logic gates driving coupled resistive--capacitive interconnections [J] . Kevin T. Tang, Eby G. Friedman Integration . 2000,第2期

机译：CMOS逻辑门驱动耦合电阻-电容互连的延迟和噪声估计
2. The effect of signal activity on propagation delay of CMOS logic gates driving coupled on-chip interconnections [J] . Kevin T. Tang, Eby G. Friedman Analog Integrated Circuits and Signal Processing . 2002,第3期

机译：信号活动对驱动耦合的片上互连的CMOS逻辑门的传播延迟的影响
3. Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs [J] . Allstot D.J., San-Hwa Chee IEEE Transactions on Circuits and Systems. 1 . 1993,第9期

机译：适用于低噪声混合信号IC的折叠式源极耦合逻辑与CMOS静态逻辑
4. Design of Universal logic gates and Majority Gate Using One clock pulse based CMOS Capacitor Coupled Threshold Logic [C] . Arpita Dey, Mili Sarkar, Riddhi Roy, IEEE International IOT, Electronics and Mechatronics Conference . 2020

机译：基于一个时钟脉冲的CMOS电容耦合门限逻辑设计通用逻辑门和多数门
5. CMOS logic gate simulation using a physically-derived large-signal nonquasi-static MOSFET model. [D] . Palanichamy, Chandra. 2008

机译：使用物理衍生的大信号非准静态MOSFET模型进行CMOS逻辑门仿真。
6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
7. Leakage Tolerant, Noise Immune domino logic for circuit design in the ultra deep sub-micron CMOS technology for haigh fan-in gates [O] . Peiravi, Ali, Moradi, Farshad, Wisland, Dag T 2009

机译：用于高风扇门的超深亚微米CmOs技术中的电路设计的漏电容，噪声免疫多米诺逻辑

Noise Estimation Due To Signal Activity For Capacitively Coupled CMOS Logic Gates

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