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Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

机译：嵌入式MPSoC的L2片上高速缓存架构的性能和能量折衷分析

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Mohamed M. Sabry; Martino Ruggiero; Pablo G. Del Valle;
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年度 2012
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机译：可重新配置的嵌入式MPSoC中用于能耗的两级缓存调整技术
2. A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches [J] . Mittal Sparsh, Vetter Jeffrey S., Li Dong Parallel and Distributed Systems, IEEE Transactions on . 2015,第6期

机译：管理嵌入式DRAM和非易失性片上高速缓存的体系结构方法的概述
3. Energy Efficient Caching-on-Cache Architectures for Embedded Systems [J] . HUNG-CHENG WU, TIEN-FU CHEN, HUNG-YU LI, Journal of information science and engineering . 2003,第5期

机译：嵌入式系统的节能高速缓存架构
4. Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs [C] . Mohamed M. Sabry, Martino Ruggiero, Pablo G. Del Valle 20th great lakes symposium on VLSI 2010 (GLSVLSI 2010) . 2010

机译：嵌入式MPSoC的L2片上高速缓存架构的性能和能量折衷分析
5. Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures. [D] . Coddington, James David. 2015

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8. On-Chip Instruction Caches for High Performance Processors [R] . Agarwal, A., Chow, P., Horowitz, M., 1987

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Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

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