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Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance

机译：基于价值的时钟门控和操作打包：用于提高处理器功率和性能的动态策略

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David Brooks; Margaret Martonosi;
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年度 2000
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1. Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance [J] . David Brooks, Margaret Martonosi ACM transactions on computer systems . 2000,第2期

机译：基于价值的时钟门控和操作打包：用于提高处理器功率和性能的动态策略
2. A Virtual Impedance Control Strategy for Improving the Stability and Dynamic Performance of VSC–HVDC Operation in Bidirectional Power Flow Mode [J] . Yuye Li, Kaipei Liu, Xiaobing Liao, Applied Sciences . 2019,第15期

机译：一种虚拟阻抗控制策略，用于提高双向动力流模式下VSC-HVDC操作的稳定性和动态性能
3. Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling [J] . Akira MOCHIZUKI, Daisuke NISHINOHARA, Takahiro HANYU IEICE Transactions on Electronics . 2004,第11期

机译：具有动态电源电压/时钟频率缩放比例的通过门逻辑的低功耗运动矢量检测VLSI处理器
4. Adaptive clocking with dynamic power gating for mitigating energy efficiency performance impacts of fast voltage droop in a 22nm graphics execution core [C] . Minki Cho, Carlos Tokunaga, Stephen Kim, Symposium on VLSI Circuits . 2016

机译：具有动态功率门控功能的自适应时钟可减轻22nm图形执行内核中快速电压下降对能源效率和性能的影响
5. Power and Timing Driven Optimal Gate, Clock Buffer and Clock Wire Sizing in High Performance Digital Integrated Circuits [D] . Farshidi, Amin. 2016

机译：功率和定时驱动最佳栅极，时钟缓冲器和时钟线寸在高性能数字集成电路中尺寸
6. Analytical Modeling of In-Process Temperature in Powder Bed Additive Manufacturing Considering Laser Power Absorption Latent Heat Scanning Strategy and Powder Packing [O] . Jinqiang Ning, Daniel E. Sievers, Hamid Garmestani, 2019

机译：考虑激光功率吸收潜热扫描策略和粉末填充的粉末床增材制造过程中温度的分析模型
7. Priority Assignment Optimization for Minimization of Current Surge in High Performance Power Efficient Clock-gated Microprocessor [O] . 2008

机译：优先级分配优化，可最大限度地降低高性能节能时钟门控微处理器中的电流浪涌

Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance

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