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Performance and Power Effectiveness in Embedded Processors -- Customizable Partitioned Caches

机译：嵌入式处理器的性能和电源效率-可自定义的分区缓存

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Peter Petrov; Alex Orailoglu;
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年度 2001
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1. LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors [J] . Gracia D. S. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2012,第8期

机译：LP-NUCA：高性能低功耗嵌入式处理器的缓存网络
2. Low-cost and power-efficient thread collision detection scheme for shared caches in a real-time multithreaded embedded processor [J] . EMRE ?ZER Turkish Journal of Electrical Engineering and Computer Sciences . 2013,第3期

机译：实时多线程嵌入式处理器中共享缓存的低成本，高能效线程冲突检测方案
3. An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors [J] . CheolHong KIM, SungWoo CHUNG, ChuShik JHON IEICE Transactions on Information and Systems . 2006,第4期

机译：嵌入式处理器的节能分区指令缓存体系结构
4. Towards effective embedded processors in codesigns: customizable partitioned caches [C] . Petrov, P., Orailoglu, Hardware/Software Codesign, 2001. CODES 2001. Proceedings of the Ninth International Symposium on . 2001

机译：迈向代码符号中的有效嵌入式处理器：可定制的分区缓存
5. Cross-layer customization for low power and high performance embedded multi-core processors. [D] . Yu, Chenjie. 2010

机译：用于低功耗和高性能嵌入式多核处理器的跨层定制。
6. An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture [O] . Wenheng Ma, Qiao Cheng, Yudi Gao, 2021

机译：具有可变微型架构的超低功耗嵌入式处理器
7. Towards effective embedded processors in codesigns: Customizable partitioned caches [O] . Peter Petrov, Alex Orailoglu 2001

机译：迈向代码签名中的有效嵌入式处理器：可自定义的分区缓存

Performance and Power Effectiveness in Embedded Processors -- Customizable Partitioned Caches

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