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Using Formal Verification Techniques to Reduce Simulation and Test Effort

机译：使用形式验证技术减少仿真和测试工作量

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O. Laurent; P. Michel; V. Wiels;
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年度 2007
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1. Simulation-Based Approaches for Verification of Embedded Control Systems: An Overview of Traditional and Advanced Modeling, Testing, and Verification Techniques [J] . James Kapinski, Jyotirmoy V. Deshmukh, Xiaoqing Jin, Control Systems, IEEE . 2016,第6期

机译：嵌入式控制系统的基于仿真的验证方法：传统和高级建模，测试和验证技术的概述
2. An improved genetic algorithm for task scheduling in the cloud environments using the priority queues: Formal verification, simulation, and statistical testing [J] . Bahman Keshanchi, Alireza Souri, Nima Jafari Navimipour The Journal of Systems and Software . 2017,第FEBa期

机译：一种改进的遗传算法，用于使用优先级队列在云环境中进行任务调度：形式验证，模拟和统计测试
3. Reducing verification effort in component-based software engineering through built-in testing [J] . Daniel Brenner, Colin Atkinson, Rainer Malaka, Information systems frontiers . 2007,第2a3期

机译：通过内置测试减少基于组件的软件工程中的验证工作
4. Using Formal Verification Techniques to Reduce Simulation and Test Effort [C] . O. Laurent, P. Michel, V. Wiels International Symposium of Formal Methods Europe, Mar 12-16, 2001, Berlin, Germany . 2001

机译：使用形式验证技术减少仿真和测试工作量
5. Applications of Formal And Semi-formal Verification on Software Testing, High-level Synthesis And Energy Internet [D] . Gao, Min. 2018

机译：正式和半正式验证在软件测试，高级综合和能源互联网中的应用
6. Numerical Simulations of Realistic Lead Trajectories and an Experimental Verification Support the Efficacy of Parallel Radiofrequency Transmission to Reduce Heating of Deep Brain Stimulation Implants during MRI [O] . C. E. McElcheran, L. Golestanirad, M. I. Iacono, -1

机译：现实的铅轨迹的数值模拟和实验验证支持并行射频传输减少MRI期间深部脑刺激植入物发热的功效
7. Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms [O] . Meng Zhang, Anita Lungu, Daniel J. Sorin 2015

机译：不同容错机制的形式验证和测试努力分析

Using Formal Verification Techniques to Reduce Simulation and Test Effort

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