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Repeater Insertion combined with LGR Methodology for on-Chip Interconnect Timing Optimization

机译：中继器插入与LGR方法结合用于片上互连时序优化

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Michael Moreinis; Arkadiy Morgenshtein; Israel A. Wagner; Avinoam Kolodny;
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年度 2012
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1. A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects [J] . Falah R. Awwad, Mohamed Nekili, Mohamad Sawan International journal of circuit theory and applications . 2012,第7期

机译：长片上互连的并行中继器插入方法的新理论
2. A Novel Low Power High Dynamic Threshold Swing Limited Repeater Insertion for On-Chip Interconnects [J] . International Journal of VLSI Design & Communication Systems . 2014,第6期

机译：片上互连的新型低功耗高动态门限摆动受限中继器插入
3. Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization [J] . Moreinis M., Morgenshtein A., Wagner I. A., IEEE transactions on very large scale integration (VLSI) systems . 2006,第期

机译：逻辑门作为中继器（LGR），用于区域有效的时序优化
4. Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization [C] . Moreinis M., Morgenshtein A., Wagner I.A., Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on . 2004

机译：中继器插入结合LGR方法进行片上互连时序优化
5. A theory on repeater-insertion methodologies for SoC interconnects. [D] . Awwad, Falah Rashad. 2006

机译：SoC互连的中继器插入方法论。
6. Development of a Non-Invasive On-Chip Interconnect Health Sensing Method Based on Bit Error Rates [O] . Insun Shin, Kyoungmin Koo, Daeil Kwon 2018

机译：基于误码率的非侵入式片上互连健康感测方法的开发
7. _ Noise-aware Repeater Insertion and Wire Sizing for On-chip Interconnect Using Hierarchical Moment-Matching [O] . 2013

机译：_噪声感知中继器插入和使用分级矩匹配的片上互连导线尺寸

Repeater Insertion combined with LGR Methodology for on-Chip Interconnect Timing Optimization

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