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Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures

机译：动态验证高速缓存一致性多线程计算机体系结构中的内存一致性

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Albert Meixner; Student Member; Daniel J. Sorin; Senior Member;
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年度 2006
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1. Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures [J] . Meixner Albert, Sorin Daniel J. Dependable and Secure Computing, IEEE Transactions on . 2009,第1期

机译：缓存一致的多线程计算机体系结构中内存一致性的动态验证
2. TLB Update-Hint: A Scalable TLB Consistency Algorithm for Cache-Coherent Non-uniform Memory Access Multiprocessors [J] . Byeonghag SEONG, Donggook KIM, Yangwoo ROH, IEICE Transactions on Information and Systems . 2004,第7期

机译：TLB更新提示：用于缓存一致的非均匀内存访问多处理器的可扩展TLB一致性算法
3. Design verification of the S3.mp cache-coherent shared-memory system [J] . Fong Pong, Browne M. IEEE Transactions on Computers . 1998,第1期

机译：S3.mp缓存一致性共享内存系统的设计验证
4. Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures [C] . Meixner, A., Sorin, . 2006

机译：高速缓存一致性多线程计算机体系结构中内存一致性的动态验证
5. Progressive Automated Formal Verification of Memory Consistency in Parallel Processors [D] . Manerkar, Yatin Avdhut. 2021

机译：逐行自动验证并行处理器中内存一致性的正式验证
6. Memory and Energy Optimization Strategies for Multithreaded Operating System on the Resource-Constrained Wireless Sensor Node [O] . Xing Liu, Kun Mean Hou, Christophe de Vaulx, 2015

机译：资源受限的无线传感器节点上多线程操作系统的内存和能量优化策略
7. Specifying and Dynamically Verifying Address Translation-Aware Memory Consistency [O] . Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin 2010

机译：指定并动态验证地址转换感知内存一致性

Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures

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