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Dry Etching of High-K Dielectric PZT Stacks for Integrated Passive Devices

机译：用于集成无源器件的高K电介质PZT叠层的干法刻蚀

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Genevieve Beique; John Almerico; Robert Ditizio; Guillaume Guegan; Jean Philipe Queniot;
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年度 2008
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1. Dry Etching of High-K Dielectric PZT Stacks for Integrated Passive Devices [J] . Genevieve Beique, John Almerico, Robert Ditizio Integrated Ferroelectrics . 2006,第1期

机译：用于集成无源器件的高K电介质PZT叠层的干法刻蚀
2. Etching titanium nitride gate stacked on high-k dielectric [J] . J.C. Gerharz, K. Padmaraju, J. Moers D. Griitzmacher Microelectronic Engineering . 2011,第8期

机译：蚀刻堆叠在高k电介质上的氮化钛栅极
3. Dry-etching properties of TiN for metal/high-k gate stack using BCl3-based inductively coupled plasma [J] . Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films . 2009,第6期

机译：基于BCl3的电感耦合等离子体对金属/高k栅堆叠TiN的干法刻蚀性能
4. Effects of nitrogen additive gas on sidewall passivation in W/TiN/high-k dielectric gate etching [C] . Jae-Young Kim, Yu-Kwon Kim . 2000

机译：氮气对W / TiN /高k介质栅刻蚀中侧壁钝化的影响
5. Tantalum oxide as an alternative dielectric material for polyimide integrated passive devices and dynamic random access memory applications. [D] . Tang, Derek Manto. 2010

机译：氧化钽可作为聚酰亚胺集成无源器件和动态随机存取存储器应用的替代介电材料。
6. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure [O] . Szu-Hung Chen, Wen-Shiang Liao, Hsin-Chia Yang, 2012

机译：具有纳米堆叠的高k栅极电介质和3D鳍形结构的高性能III-V MOSFET
7. Hf-based high-K gate dielectric and metal gate stack for advanced CMOS devices [O] . JOO MOON SIG 2006

机译：基于Hf的高K栅极电介质和金属栅极叠层，用于高级CMOS器件

Dry Etching of High-K Dielectric PZT Stacks for Integrated Passive Devices

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