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A 3D NETWORK-ON-CHIP FOR STACKED-DIE TRANSACTIONAL CHIP MULTIPROCESSORS USING THROUGH SILICON VIAS

机译：硅晶片通过叠层交易芯片多处理器的3D芯片网络

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Sumeet S. Kumar; Rene Van Leuken;
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年度 2014
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1. A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias [J] . Said Mostafa, Shalaby Ahmed, Mehdipour Farhad, Microprocessors and microsystems . 2016,第JUNa期

机译：具有多重硅通孔的3D片上网络的设计方法以及各种性能和制造指标评估
2. Photonic Network-on-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessors [J] . ALEKSANDR BIBERMAN, KYLE PRESTON, GILBERT HENDRY, ACM Journal on Emerging Technologies in Computing Systems . 2011,第2期

机译：使用多层沉积硅材料的高性能芯片多处理器光子片上网络体系结构
3. Transaction Ordering in Network-on-Chips for Post-Silicon Validation [J] . Amir Masoud GHAREHBAGHI, Masahiro FUJITA IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2012,第12期

机译：片上网络中的交易顺序以进行硅后验证
4. A 3D Network-on-Chip for stacked-die transactional chip multiprocessors using Through Silicon Vias [C] . Kumar Sumeet S., van Leuken Rene 6th International Conference on Design and Technology of Integrated Systems in Nanoscale Era . 2011

机译：使用硅通孔的堆叠式芯片交易芯片多处理器的3D片上网络
5. Dynamic Lifetime Reliability and Energy Management for Network-on-Chip Based Chip Multiprocessors [D] . Ghorbani Moghaddam, Milad. 2018

机译：基于片上网络的芯片多处理器的动态寿命可靠性和能量管理
6. Fabrication and Optimization of High Aspect Ratio Through-Silicon-Vias Electroplating for 3D Inductor [O] . Haiwang Li, Jiasi Liu, Tiantong Xu, 2018

机译：用于3D电感器的高长宽比硅-Vias电镀的制备和优化
7. A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias [O] . Said, M., Shalaby, A., Madipour, Farhad, 2017

机译：具有多重硅通孔的3D片上网络的设计方法以及各种性能和制造指标评估

A 3D NETWORK-ON-CHIP FOR STACKED-DIE TRANSACTIONAL CHIP MULTIPROCESSORS USING THROUGH SILICON VIAS

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