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Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

机译：架构和编译器支持，以减少高性能微处理器的内存层次结构中的能耗

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Nikolaos Bellas; Ibrahim Hajj; Constantine Polychronopoulos; George Stamoulist;
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年度 1998
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专利

1. Architectural and compiler techniques for energy reduction inhigh-performance microprocessors [J] . Bellas N., Hajj I.N., Polychronopoulos C.D., IEEE transactions on very large scale integration (VLSI) systems . 2000,第3期

机译：架构和编译器技术，可降低高性能微处理器的能耗
2. Architectural and compiler techniques for energy reduction in high-performance microprocessors [J] . Bellas N., Hajj I.N. IEEE transactions on very large scale integration (VLSI) systems . 2000,第3期

机译：架构和编译器技术，可降低高性能微处理器的能耗
3. DYNAMIC-COMPILER-DRIVEN CONTROL FOR MICROPROCESSOR ENERGY AND PERFORMANCE [J] . Qiang Wu, Margaret Martonosi, Douglas W. Clark, IEEE Micro . 2006,第1期

机译：微处理机能量和性能的动态比较器驱动控制
4. Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors [C] . Nikolaos Bellas Ibrahim Hajj, George Stamoulis, N. Bellas, International symposium on Low power electronics and design . 1998

机译：架构和编译器支持可减少高性能微处理器的内存层次结构中的能耗
5. Architectural and compiler techniques for energy reduction in high-performance microprocessors. [D] . Bellas, Nikolaos. 1999

机译：用于降低高性能微处理器能耗的体系结构和编译器技术。
6. Hierarchical and hybrid energy storage devices in data centers: Architecture control and provisioning [O] . Mengshu Sun, Yuankun Xue, Paul Bogdan, -1

机译：数据中心中的分层和混合式能量存储设备：架构控制和配置
7. Architectural and compiler techniques for energy reduction in high-performance microprocessors [O] . Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, 2000

机译：用于高性能微处理器中的能量减少的架构和编译器技术

Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

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