首页> 外文OA文献 >Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs

【2h】

Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs

机译：用户指定的输入序列和程序下顺序逻辑电路功率估计的技术

页面导航

著录项
引文网络
相似文献
相关主题

著录项

作者
José Monteiro; Srinivas Devadas;
展开▼
作者单位

展开▼
年度 1994
总页数
原文格式 PDF
正文语种
中图分类

相似文献

外文文献
中文文献
专利

1. Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence] [J] . Chi-Ying Tsui, Monteiro J. IEEE transactions on very large scale integration (VLSI) systems . 1996,第4期

机译：对“顺序逻辑电路的功率估算方法”的更正[对应]
2. Power estimation methods for sequential logic circuits [J] . Chi-Ying Tsui, Monteiro J. IEEE transactions on very large scale integration (VLSI) systems . 1995,第3期

机译：时序逻辑电路的功率估算方法
3. Power estimation methods for sequential logic circuits [J] . Chi-Ying Tsui, Monteiro J., Massoud Pedram, IEEE transactions on very large scale integration (VLSI) systems . 1995,第3期

机译：时序逻辑电路的功率估算方法
4. Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs [C] . Jose Monteiro, Srinivas Devadas Proceedings of the 1995 international symposium on Low power design . 1995

机译：用户指定输入序列和程序下顺序逻辑电路功率估计的技术
5. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures. [D] . Tang, Aoxiang. 2015

机译：低功耗FinFET逻辑电路和架构的延迟/功率建模和优化技术。
6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
7. Design of Low Power CMOS Logic Circuits Using Gate Diffusion Input (GDI) Technique [O] . Y. Syamala, K. Srilakshmi, N. Somasekhar Varma 2013

机译：利用门扩散输入（GDI）技术设计低功耗CMOS逻辑电路

Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs

著录项

引文网络

相似文献

相关主题

期刊订阅