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Instruction Packing: Reducing Power and Delay of the Dynamic Scheduling Logic

机译：指令打包：降低动态调度逻辑的功耗和延迟

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Joseph J. Sharkey; Dmitry V. Ponomarev; Kanad Ghose;
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年度 2005
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1. Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping [J] . Sasaki H., Kondo M., Nakamura H. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2009,第6期

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2. Reducing Power and Delay in Instruction Queue for Sram Based Processor Unit [J] . G. Dhanalakshmi, M. Sundarambal, K. Muralidharan Asian Journal of Information Technology . 2016,第11期

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3. Dynamic Power Allocation and User Scheduling for Power-Efficient and Delay-Constrained Multiple Access Networks [J] . Choi Minseok, Kim Joongheon, Moon Jaekyun IEEE transactions on wireless communications . 2019,第10期

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4. Instruction packing: reducing power and delay of the dynamic scheduling logic [C] . Sharkey, J.J., Ponomarev, . 2005

机译：指令打包：降低功耗并减少动态调度逻辑的延迟
5. The dynamics of float, logic, resource allocation, and delay timing in forensic schedule analysis and construction delay claims. [D] . Nguyen, Long duy. 2007

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6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

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7. Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources* [O] . Dmitry Ponomarev Gurhan, Dmitry Ponomarev, Gurhan Kucuk, 100

机译：通过多个数据路径资源的动态分配降低指令调度的功率要求*

Instruction Packing: Reducing Power and Delay of the Dynamic Scheduling Logic

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