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Loop-Based Inductance Extraction and Modeling for Multiconductor On-Chip Interconnects

机译：多导体片上互连的基于环路的电感提取和建模

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Sunil Yu; Student Member; Dusan M. Petranovic; Shoba Krishnan; Kwyro Lee; Senior Member; Cary Y. Yang;
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年度 2008
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1. Loop-Based Inductance Extraction and Modeling for Multiconductor On-Chip Interconnects [J] . Sunil Yu, Dusan M. Petranovic, Shoba Krishnan, IEEE Transactions on Electron Devices . 2006,第1期

机译：多导体片上互连的基于环路的电感提取和建模
2. A multiconductor transmission line methodology for global on-chip interconnect modeling and analysis [J] . Elfadel I.M., Deutsch A., Smith H.H., IEEE Transactions on Advanced Packaging . 2004,第1期

机译：用于全球片上互连建模和分析的多导体传输线方法
3. Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects [J] . Atsushi KUROKAWA, Kotaro HACHIYA, Takashi SATO, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2003,第4期

机译：包括角度互连的VLSI的快速片上电感提取
4. On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation [C] . Xiaoning Qi, Gaofeng Wang . 2000

机译：VLSI互连的片上电感建模和RLC提取用于电路仿真
5. On-chip inductance extraction, simulation and modeling. [D] . Hu, Haitian. 2002

机译：片上电感提取，仿真和建模。
6. Development of a Non-Invasive On-Chip Interconnect Health Sensing Method Based on Bit Error Rates [O] . Insun Shin, Kyoungmin Koo, Daeil Kwon 2018

机译：基于误码率的非侵入式片上互连健康感测方法的开发
7. On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation [O] . R.W. Dutton, N. Chang -1

机译：电路模拟VLSI互连的片上电感建模和RLC提取

Loop-Based Inductance Extraction and Modeling for Multiconductor On-Chip Interconnects

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