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Performance Optimization of VLSI Interconnect Layout

机译：VLSI互连布局的性能优化

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Jason Cong; Lei He; Cheng-Kok Koh; Patrick H. Madden;
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年度 1996
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1. An Optimization Algorithm Based On Grid-Graphs For Minimizing Interconnect Delay In VLSI Layout Design [J] . Mohamed Khalil Hani, Nasir Shaikh-Husin Malaysian Journal of Computer Science . 2009,第1期

机译：VLSI布局设计中基于网格图的互连延迟最小优化算法
2. Designing of ultra-low-power high-speed repeaters for performance optimization of VLSI interconnects at 32 nm [J] . Khursheed Afreen, Khare Kavita, Haque Fozia Zia International journal of numerical modelling . 2019,第2期

机译：设计超低功耗高速转发器，以优化32 nm的VLSI互连的性能
3. Designing of ultra-low-power high-speed repeaters for performance optimization of VLSI interconnects at 32 nm [J] . Khursheed Afreen, Khare Kavita, Haque Fozia Zia International journal of numerical modelling . 2019,第2期

机译：设计超低功耗高速中继器，用于32nm的VLSI互连的性能优化
4. Simultaneous Routing and Buffer Insertion Algorithm for Interconnect Delay Optimization in VLSI Layout Design [C] . Mohamed Khalil Hani, Nasir Shaikh-Husin International Conference on Microelectronics . 2008

机译：VLSI布局设计中互连延迟优化的同时路由和缓冲插入算法
5. VLSI interconnect layout optimization. [D] . Koh, Cheng-Kok. 1998

机译：VLSI互连布局优化。
6. Systematic Layout Planning of a Radiology Reporting Area to Optimize Radiologists’ Performance [O] . Guilherme Brittes Benitez, Flavio Sanson Fogliatto, Ricardo Bertoglio Cardoso, 2018

机译：放射报告区域的系统布局规划以优化放射医师的表现
7. An optimization algorithm based on grid-graphs for minimizing interconnect delay in VLSI layout design [O] . Mohd. Hani Mohamed Khalil, Shaikh Husin Nasir 2009

机译：一种基于网格图的优化算法，可最大程度地减少VLSI布局设计中的互连延迟
8. Timing and Area Optimization for VLSI Circuit and Layout. [R] . Chuang, W. T. 1994

机译：VLsI电路和布局的时序和面积优化。

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