A radiation tolerant testbed was designed using a Commercial-Off-the- Self Digital Signal Processor and presented to prove the concept of Triple Modular Redundant (TMR) processors in order to make a COTS DSP radiation tolerant design. The system was designed to handle the effects of radiation associated with Single Event Upset only. Two of the industry's leading programmable 32-bit floating-point digital signal processors were reviewed for this thesis, Analog Devices ADSP-21060 and the Texas Instruments TMS320C6701. The 6701 was the best processor for this design based upon size, power, speed, and tolerance to single event latchup, signal event burnout, and total ionization dose. A review of the processor's performance and characteristics is provided to ensure the proper operation of 6701 in a TMR design. The system employs a bit by bit voter that compares the three processors' results and outputs the majority of the bits. All data, address, and control signals are monitored to determine that the system is operating properly. This system significantly differs from previous TMR designs, because only address errors cause immediate interrupts. Data errors cause processor interrupts only when the errors accumulate to a critical level. An external host processor controls the processors' shared memory space.
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