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Design of Hardware Accelerators with Configurable Pipeline

机译:可配置管道的硬件加速器设计

摘要

In today’s world, people are widely using technology to make their lives more comfortable and better. The development of semiconductors technology is making Integrated Circuits(IC) smaller and smaller in size, thus allowing IC designer to include more and more functionalities in their products. This development of technology has allowed a large diffusion of semiconductor devices in all aspects of human life, leading to the concept of “embedded” computation, described as the practice of including the small processor devices in all spaces of our world, from our houses, to our cars, to even “wearable electronics” that we carry around as we move. In particular, floating point computation (FP) is a feature of computers that, at the price of significant additional hardware complexity and sometimes at the price of result accuracy, provides a much larger range of usable numbers, thus significantly enhancing the flexibility and usability of our computation. The additional hardware complexity imposed by FP units imposed a relevant price in Silicon Area (making the IC more expensive) and especially in terms of power consumption. In turn, energy consumption is a very severe issue in semiconductor technologies: first, it causes unreliability of the IC technology. Secondly, IC energy consumption leads to greenhouse gas emission. Finally, many IC systems are battery operated and high consumption may jeopardize the system usability and/or user experience. One very significant category of embedded processors is that of embedded sensors. Embedded sensors produce relevant quantities of raw data that needs to be adequately classified in order to provide significant information, and Machine Learning is often applied as a strategy for sensor data classification.This MENG project aims at exploring design strategies for low-power FP computation. In the following, we will introduce the design of a hardware FPU unit whose sub-blocks can be programmed to change dynamically the computational speed with the change in the voltage. This enables the FPU to adapt their consumption to the requirement of the environment, offering high performance (and high consumption) whenever needed by the environment, but adapting to low power, low speed mode whenever intensive processing is not necessary.
机译:在当今世界,人们广泛使用技术来使自己的生活更舒适,更好。半导体技术的发展正在使集成电路(IC)的尺寸越来越小,从而使IC设计人员能够在其产品中包含越来越多的功能。这项技术的发展已使半导体设备在人类生活的各个方面大量传播,从而导致了“嵌入式”计算的概念,这种概念被描述为在我们的房屋中,将小型处理器设备包括在我们世界的所有空间中,到我们的汽车,甚至是我们随身携带的“可穿戴电子产品”。特别地,浮点计算(FP)是计算机的一项功能,它以极大的额外硬件复杂性为代价,有时以结果精度为代价,提供了更大范围的可用数字,从而显着增强了灵活性和可用性。我们的计算。 FP单元带来的额外硬件复杂性在Silicon Area中增加了相关价格(使IC更加昂贵),尤其是在功耗方面。反过来,能耗是半导体技术中非常严重的问题:首先,它导致IC技术的可靠性。其次,集成电路的能耗导致温室气体排放。最后,许多IC系统是电池供电的,高功耗可能会危害系统的可用性和/或用户体验。嵌入式处理器的一个非常重要的类别是嵌入式传感器。嵌入式传感器产生大量的原始数据,需要对其进行适当分类以提供重要信息,并且机器学习通常被用作传感器数据分类的策略.MENG项目旨在探索低功耗FP计算的设计策略。在下文中,我们将介绍硬件FPU单元的设计,该单元的子块可以编程为随着电压的变化而动态地改变计算速度。这使FPU可以使其消耗适应环境要求,在环境需要时提供高性能(和高消耗),但是在不需要密集处理时可以适应低功耗,低速模式。

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    Kaur Gurveer;

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  • 年度 2016
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