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Design of Interface Circuits for Capacitive Sensing Applications

机译:电容传感应用的接口电路设计

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摘要

This thesis focuses on the design of integrated readout circuits for differential capacitive sensing applications. Such circuits are needed especially for interfacing with microsensors where capacitive transduction is predominantly used. The result of this research is the development of common framework for interface circuitries suitable for different sensing applications. These interface circuits were designed and fabricated in standard Complementary Metal-Oxide-Semiconductor (CMOS) processes and can be integrated into the design of various sensing systems. The proposed circuits in this work are characterized by high dynamic range, low power consumption, and adjustable sensing range. Such circuits promote easy-to-use user interfaces while having a low cost. Three different circuit designs were proposed and form the highlights of this thesis. The first interface circuit is a novel realization of a synchronous demodulation technique. The main advantage of the proposed circuit compared to state-of-the-art is that it has a high sensing dynamic range of 112dB and is capable of measuring capacitance as small as 30 aF with a total power consumption of 8mW. Low power consumption is one of the most important design criteria for portable sensing systems besides accuracy and precision. Following this requirement, low power consumption is the main criterion in the second circuit proposed in this work. This circuit uses a switch-based capacitance-to-voltage converter that is designed and fabricated in 0.35μm CMOS technology. This circuit had a low power consumption of 600μW. Its simple structure offers area and power advantages over the more complex circuits. In addition, its ratiometric sensing feature provides an adjustable sensing range which can be tuned for different applications. This circuit can detect capacitances as small as 230 aF in 1pF range of capacitance. To reduce the effect of parasitics on the circuit performance and improve the linearity, the design of the second circuit was enhanced. By using an additional block and an analog divider, the sensitivity of the circuit to parasitics was significantly reduced. On the other hand, a time based output allowed for the elimination of the analog buffers. The fabricated circuit consumed a total power of only 720μW and was fabricated in 0.35μm CMOS technology. Another advantage of this circuit over the previous designs is that the pulse-width output signal of this circuit can be more easily digitized. The proposed circuits in this thesis have been tested with different types of sensors including humidity, motion, and variable MEMS capacitors. For all of them also, the measurement results are found to be in good agreement with the analytic and simulation results. These circuits can be used as standalone chips or can be integrated into the design of larger sensing systems.
机译:本文主要研究用于差分电容传感应用的集成读出电路。特别是与主要使用电容转导的微传感器接口时,需要这样的电路。这项研究的结果是开发适用于不同传感应用的接口电路通用框架。这些接口电路是采用标准的互补金属氧化物半导体(CMOS)工艺设计和制造的,可以集成到各种传感系统的设计中。在这项工作中提出的电路具有高动态范围,低功耗和可调节感测范围的特点。这样的电路促进了易于使用的用户界面,同时具有低成本。提出了三种不同的电路设计,它们构成了本文的重点。第一接口电路是同步解调技术的新颖实现。与最新技术相比,该电路的主要优势在于它具有112dB的高感测动态范围,并能够测量小至30 aF的电容,总功耗为8mW。除精度和精度外,低功耗是便携式传感系统最重要的设计标准之一。遵循这一要求,低功耗是这项工作提出的第二电路的主要标准。该电路使用基于开关的电容电压转换器,该转换器采用0.35μmCMOS技术进行设计和制造。该电路具有600μW的低功耗。与更复杂的电路相比,其简单的结构在面积和功率方面都具有优势。此外,它的比例感测功能提供了可调节的感测范围,可以针对不同的应用进行调整。该电路可以在1pF的电容范围内检测到230 aF的电容。为了减少寄生效应对电路性能的影响并提高线性度,第二电路的设计得到了增强。通过使用一个附加模块和一个模拟分频器,电路对寄生的灵敏度大大降低。另一方面,基于时间的输出可消除模拟缓冲区。所制造的电路仅消耗了720μW的总功率,并采用0.35μmCMOS技术制造。与以前的设计相比,该电路的另一个优点是该电路的脉冲宽度输出信号可以更容易地数字化。本文中提出的电路已通过不同类型的传感器(包括湿度,运动和可变MEMS电容器)进行了测试。对于所有这些,测量结果与分析和仿真结果也非常吻合。这些电路可以用作独立芯片,也可以集成到较大的传感系统的设计中。

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    Aezinia Fatemeh;

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  • 年度 2014
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