The Advanced Encryption Standard (AES) was approved in 2001 and has been used since then. It is more computationally robust compared with previous algorithms, providing a higher level of security. However, it needs more time to execute due to the long calculation and several iterations. The goal of this thesis is to study AES and develop a new hardware algorithm for the most time consuming section of AES to improve the performance. Custom circuits are designed mainly to reduce the area of the circuit. Custom circuits are implemented by VHDL, Synopsys and Encounter. Results show that custom designs bring area reduction up to 68%, and power reduction up to 20%. The reduced area brought by the custom designs allows the T-BOX architecture, which has a higher throughput rate than the S-BOX architecture to compensate the drawback of occupying more area than S-BOX does.
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