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Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators

机译：双量化delta-sigma调制器中模拟积分器非理想性的影响和补偿

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Graduation date: 1993

机译：毕业日期：1993

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年度 1993
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1. Multibit Delta-Sigma Architectures with Two-Level Feedback Loop Using a Dual-Quantization Architecture [J] . Noboru Sakimura, Motoi Yamaguchi, Michio Yotsuyanagi IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2001,第2期

机译：使用双量化架构的具有两级反馈回路的多位Delta-Sigma架构
2. A 20-MHz bandwidth, 75-dB dynamic range, continuous-time delta-sigma modulator with reduced nonidealities [J] . Song Seokjae, Lee Jaeseong, Roh Jeongjin International journal of circuit theory and applications . 2019,第8期

机译：20 MHz带宽，75 dB动态范围，连续时间的delta-sigma调制器，具有降低的非理想性
3. A 20-MHz bandwidth, 75-dB dynamic range, continuous-time delta-sigma modulator with reduced nonidealities [J] . Song Seokjae, Lee Jaeseong, Roh Jeongjin International journal of circuit theory and applications . 2019,第8期

机译：一个20-MHz的带宽，75 dB动态范围，连续时间Δ-sigma调制器，具有减少的非侵入性
4. Excess loop delay effects in continuous-time delta-sigma modulators and the compensation solution [C] . Gao, W., Shoaei, . 1997

机译：连续时间delta-sigma调制器中的多余环路延迟效应和补偿解决方案
5. Continuous compensation of binary-weighted DAC nonlinearities in bandpass delta-sigma modulators. [D] . Gagnon, Ghyslain. 2009

机译：带通delta-sigma调制器中二进制加权DAC非线性的连续补偿。
6. A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate [O] . Yao Xiao, Zhifei Lu, Zhaofeng Ren, 2020

机译：具有2.4Ghz时钟速率的100Mhz带宽80dB动态范围连续时间Δ-Σ调制器
7. Signal Compensation for Analog Rotor Position Errors due to Nonideal Sinusoidal Encoder Signals [O] . Seon-Hwan Hwang, Dong-Youn Kim, Jang-Mok Kim, 2014

机译：由于非抗性正弦编码器信号引起的模拟转子位置误差的信号补偿

Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators

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