Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications

摘要

Hardware implementations of the Advanced EncryptionStandard (AES) Rijndael algorithm have recentlybeen the object of an intensive evaluation. Severalpapers describe efficient architectures for ASICs (ASIC: Application Specific Integrated Circuit)and FPGAs (FPGA: Field Programmable Gate Array). In this context, the highest effort was devotedto high throughput (up to 20 Gbps) encryptiononlydesigns, fewer works studied low area encryptiononlyarchitectures and only a few papers have investigatedlow area encryption/decryption structures.However, in practice, only a few applications needthroughput up to 20 Gbps while flexible and low costencryption/decryption solutions are needed to protectsensible data, especially for embedded hardware applications.This paper proposes an efficient solutionto combine Rijndael encryption and decryption in oneFPGA design, with a strong focus on low area constraints.The proposed design fits into the smallest XilinxFPGAs (Xilinx Spartan-3 XC3S50), deals with data streams of 208 Mbps,uses 163 slices and 3 RAM blocks and improves by68% the best-known similar designs in terms of ratioThroughput=Area. We also propose implementationsin other FPGA Families (Xilinx Virtex-II) andcomparisons with similar DES, triple-DES and AESimplementations.