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Implementing Critical Sections with the Shared Explicit Cache System in the Shared Memory Parallel Architectures

机译：在共享内存并行体系结构中使用共享显式缓存系统实现关键部分

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作者
Madajczak T.; Krawczyk H.;
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年度 2006
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原文格式 PDF
正文语种 eng
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1. Cache write generate for parallel image processing on shared memory architectures [J] . Wittenbrink C.M., Somani A.K. IEEE Transactions on Image Processing . 1996,第7期

机译：高速缓存写入生成，用于在共享内存体系结构上进行并行图像处理
2. Parallelization Strategy for Elementary Morphological Operators on Graphs: Distance-Based Algorithms and Implementation on Multicore Shared-Memory Architecture [J] . Youkana Imane, Cousty Jean, Saouli Rachida, Journal of mathematical imaging and vision . 2017,第1期

机译：基本形态运算符对图中的并行化策略：基于距离的算法和多核共享内存架构的实现
3. CACHE COHERENCE IN CENTRALIZED SHARED MEMORY AND DISTRIBUTED SHARED MEMORY ARCHITECTURES [J] . Sujit Deshpande, Priya Ravale, Sulabha Apte International Journal on Computer Science and Engineering . 2011,第Special期

机译：集中共享内存和分布式共享内存架构中的缓存一致性
4. Taking Advantage of the SHECS-Based Critical Sections in the Shared Memory Parallel Architectures [C] . Tomasz Madajczak International Conference on Parallel Processing and Applied Mathematics . 2006

机译：利用共享内存并行架构中的基于SHECS的关键部分
5. Architecture and performance of processor-memory interconnection networks for MIMD shared memory parallel processing systems. [D] . Liu, Yue-Sheng. 1990

机译：MIMD共享内存并行处理系统的处理器-内存互连网络的体系结构和性能。
6. Performance of parallel FDTD method for shared- and distributed-memory architectures: Application tobioelectromagnetics [O] . Miguel Ruiz-Cabello N., Maksims Abaļenkovs, Luis M. Diaz Angulo, 2020

机译：共享和分布式内存架构并行FDTD方法的性能：应用脚踏电磁
7. Implementation of a primaldual method for SDP on a shared memory parallel architecture [O] . Brian Borchers, Joseph G. Young 2006

机译：SDP原始方法在共享内存并行体系结构上的实现
8. Implementation of a Parallel Unstructured Euler Solver on Shared and DistributedMemory Architectures [R] . Mavriplis, D. J., Das, R., Saltz, J., 1992

机译：在共享和分布式存储器架构上实现并行非结构化Euler求解器

Implementing Critical Sections with the Shared Explicit Cache System in the Shared Memory Parallel Architectures

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