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A Precise Multi-Channel QDC FEE utilizing FPGAs as Discriminators and Delay Elements Based on the TRB3 as TDC and Readout Platform

机译：基于TRB3作为TDC和读出平台的，利用FPGA作为鉴别器和延迟元件的精确多通道QDC FEE

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Traxler M.; Galatyuk T.; Skott P.; Thomas A.; Ugur C.; Michel J.; Kardan B.; Koenig W.; Linev S.; Neiser A.; Ott P.; Otte P.; Rost A.;
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年度 2014
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正文语种 eng
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1. Single-Event-Hardened All-Digital Delay Generator for FPGA-Based Implementation of a TDC-based readout electronics [J] . S. Balaji, S. Ramasamy Journal of instrumentation: an IOP and SISSA journal . 2017,第9期

机译：基于TDC的读出电子设备的FPGA的基于FPGA的实现的单事件硬化的全数字延迟发生器
2. Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs [J] . Wu J. Nuclear Science, IEEE Transactions on . 2010,第3期

机译：使用FPGA实现基于延迟线的TDC的几个关键问题
3. A Precise High Count-Rate FPGA Based Multi-Channel Coincidence Counting System for Quantum Photonics Applications [J] . Arabul Ekin, Paesani Stefano, Tancock Scott, Photonics Journal, IEEE . 2020,第2期

机译：一种基于精确的Quantum Photonics应用的基于高信用FPGA的多通道重合计数系统
4. 264 Channel TDC Platform applying 65 channel high precision (7.2 psRMS) FPGA based TDCs [C] . Ugur Cahit, Korcyl Grzegorz, Michel Jan, 2013 IEEE Nordic Mediterranean Workshop on Time to Digital Converters . 2013

机译：264通道TDC平台采用65通道高精度（7.2 psRMS）基于FPGA的TDC
5. A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA [O] . Mojtaba Parsakordasiabi, Ion Vornicu, Ángel Rodríguez-Vázquez, 2021

机译：基于28nm FPGA的多通道直接TOF读数的低资源TDC
6. FPGA based multi-channel TDC development [O] . Ugur C., Frühauf J., Hoffmann J., 2015

机译：基于FPGA的多通道TDC开发

A Precise Multi-Channel QDC FEE utilizing FPGAs as Discriminators and Delay Elements Based on the TRB3 as TDC and Readout Platform

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