Application-specific design of low power instruction cache hierarchy for embedded processors

摘要

Embedded systems are ubiquitous. They are often driven by batteries; therefore, low power consumption is a critical issue in embedded systems design. An embedded system usually consists of processor(s) for computing and memory components for data storage. With the growing demand for functionality, the system complexity increases, so does the memory requirement. Memory occupies a large chip area and consumes a significant portion of the overall system power. Though lots of research efforts have been devoted to the low-power design, power consumption in memory has never been beaten to death and can yet be reduced by application specific customizations.Since the processor needs to fetch instructions from memory every clock cycle, the frequent instruction fetch activity will potentially incur large memory power consumption. This thesis targets a memory hierarchy with separate caches for instructions and data, and aims to reduce the power consumption related to the memory access for instructions. We intend to reduce power on instruction buses, instruction cache, and main memory.We proposed a segmental bus-invert (SBI) encoding scheme for instruction buses and a fast search algorithm to determine bus segments such that when the bus-invert coding is applied to each segment, the overall bus switching activity can be greatly reduced and a considerable amount of bus power consumption can be saved.To reduce I-cache power consumption, we developed a novel Reduced One-Bit Tag Instruction Cache (ROBTIC) architecture and a dynamic cache mapping scheme, with which the spatial and temporal locality of the applications can be highly explored. The ROBTIC design can achieve the cache performance as high as a traditional cache but is much more power efficient.For further cache power reduction, we introduced an innovative decoded loop instruction cache (DLIC) design that is able to cache large and complex loops, so that accesses to the instruction cache are significantly decreased and the I-cache can be idle most of the time for power saving.The proposed cache performance-aware power reduction techniques effectively maintain or achieve a high cache performance, which, in turn, greatly reduces the access to the main memory, and hence the main memory power consumption.