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Suppression of Short Channel Effects(SCEs) by Dual Material Gate Vertical Surrounding Gate(DMGVSG) MOSFET: 3-D TCAD Simulation

机译：双材料栅垂直环绕栅（DMGVSG）MOSFET抑制短沟道效应（SCE）：3-D TCAD仿真

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Bhanu Chandar D.; Vadthiya Narendar; Kumar Alok; Mishra R.A.;
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年度 2013
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1. 3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects [J] . Banerjee Pritha, Sarkar Subir Kumar Journal of Computational Electronics . 2017,第3期

机译：具有双材料底栅的高k栅叠层双材料三栅极应变无硅MOSFET的3-D解析模型，可抑制短沟道效应
2. Recessed source concept in nanoscale vertical surrounding gate (VSG) MOSFETs for controlling short-channel effects [J] . Subrahmanyam B, Kumar MJ Physica, E. Low-dimensional systems & nanostructures . 2009,第4期

机译：纳米级垂直环绕栅（VSG）MOSFET中的隐式源极概念，用于控制短沟道效应
3. Analytical approach of a nanoscale triple-material surrounding gate (TMSG) MOSFETs for reduced short-channel effects [J] . P. Suveetha Dhanaselvam, N.B. Balamurugan Microelectronics journal . 2013,第5期

机译：纳米级三层材料环绕栅极（TMSG）MOSFET的分析方法，可减少短沟道效应
4. Suppression of Short Channel Effects (SCEs) by Dual Material Gate Vertical Surrounding Gate (DMGVSG) MOSFET: 3-D TCAD Simulation [C] . Bhanu Chandar D, Narendar Vadthiya, Alok Kumar International Conference on Design and Manufacturing . 2014

机译：双层材料栅极垂直周围栅极（DMGVSG）MOSFET抑制短信效应（SCES）：3-D TCAD模拟
5. Short channel effects suppression and process variability in a dual-gate Gate-All-Around Si nanowire transistor [D] . Rony, Mohammed Wahiduzzaman. 2016

机译：短沟道效应抑制和处理双栅极 - 全面Si纳米线晶体管中的过程变异性
6. Use of Bilayer Gate Insulator in GaN-on-Si Vertical Trench MOSFETs: Impact on Performance and Reliability [O] . Kalparupa Mukherjee, Carlo De Santi, Matteo Borga, 2020

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7. Analytical study of Dual Material Surrounding Gate MOSFET to suppress short-channel effects (SCEs) [O] . Arobinda Pal, Angsuman Sarkar 2014

机译：双材料环栅mOsFET抑制短沟道效应（sCEs）的分析研究

Suppression of Short Channel Effects(SCEs) by Dual Material Gate Vertical Surrounding Gate(DMGVSG) MOSFET: 3-D TCAD Simulation

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