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Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

机译：基于多峰BiCMOS-NDR电路的多值逻辑设计

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Gan Kwang-Jow; Lu Jeng-Jong; Yeh Wen-Kuan; Chen Yaw-Hwang; Chen Yan-Wun;
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年度 2016
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1. Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis [J] . MASANORI NATSUI, NAOFUMI HOMMA, TAKAFUMI AOKI, Journal of multiple-valued logic and soft computing . 2005,第5a6期

机译：基于图的进化综合设计多值逻辑电路
2. Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources [J] . Kwang-Jow GAN, Dong-Shong LIANG, Yan-Wun CHEN IEICE transactions on information and systems . 2010,第8期

机译：利用基于BiCMOS的负差分电阻电路偏置两个电流源的新型多值逻辑设计
3. Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources [J] . Kwang-Jow GAN, Dong-Shong LIANG, Yan-Wun CHEN IEICE Transactions on Information and Systems . 2010,第8期

机译：利用基于BiCMOS的负差分电阻电路（由两个电流源偏置）的新颖多值逻辑设计
4. Design of Quaternary Logic Circuits Based on Multiple-Valued Current Mode [C] . Haixia Wu, Shunan Zhong, Qilong Cai, EIEM 2011;International conference on electrical, information engineering and mechatronics . 2012

机译：基于多值电流模式的四元逻辑电路设计
5. Self-restored current-mode CMOS multiple-valued logic design and synthesis. [D] . Teng, Hsiang-Yung. 2003

机译：自恢复电流模式CMOS多值逻辑设计和综合。
6. Average output polarization dataset for signifying the temperature influence for QCA designed reversible logic circuits [O] . Md. Abdullah-Al-Shafi, Ali Newaz Bahar, Mohammad Maksudur Rahman Bhuiyan, 2018

机译：平均输出极化数据集用于表示温度对QCA设计的可逆逻辑电路的影响
7. Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits [O] . Kwang-Jow Gan, Jeng-Jong Lu, Wen-Kuan Yeh, 2016

机译：基于多峰值BiCmOs-NDR电路的多值逻辑设计

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

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