Floorplanning is an important problem in very largeudscale integrated-circuit (VLSI) design automation as it determinesudthe performance, size, yield, and reliability of VLSI chips. Fromudthe computational point of view, VLSI floorplanning is an NP-hardudproblem. In this paper, a memetic algorithm (MA) for a nonslicingudand hard-module VLSI floorplanning problem is presented. ThisudMA is a hybrid genetic algorithm that uses an effective geneticudsearch method to explore the search space and an efficient localudsearch method to exploit information in the search region. Theudexploration and exploitation are balanced by a novel bias searchudstrategy. The MA has been implemented and tested on popularudbenchmark problems. Experimental results show that the MA canudquickly produce optimal or nearly optimal solutions for all theudtested benchmark problems.
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