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FPGA implementation of an evolutionary algorithm for autonomous unmanned aerial vehicle on-board path planning

机译:自主无人飞行器机载路径规划进化算法的FPGA实现

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摘要

In this paper, a hardware-based path planning architecture for unmanned aerial vehicle (UAV) adaptation is proposed. The architecture aims to provide UAVs with higher autonomy using an application specific evolutionary algorithm (EA) implemented entirely on a field programmable gate array (FPGA) chip. The physical attributes of an FPGA chip, being compact in size and low in power consumption, compliments it to be an ideal platform for UAV applications. The design, which is implemented entirely in hardware, consists of EA modules, population storage resources, and three-dimensional terrain information necessary to the path planning process, subject to constraints accounted for separately via UAV, environment and mission profiles. The architecture has been successfully synthesised for a target Xilinx Virtex-4 FPGA platform with 32% logic slices utilisation. Results obtained from case studies for a small UAV helicopter with environment derived from LIDAR (Light Detection and Ranging) data verify the effectiveness of the proposed FPGA-based path planner, and demonstrate convergence at rates above the typical 10 Hz update frequency of an autopilot system.
机译:本文提出了一种基于硬件的无人飞行器(UAV)自适应路径规划架构。该架构旨在使用完全在现场可编程门阵列(FPGA)芯片上实现的专用进化算法(EA)为无人机提供更高的自治性。 FPGA芯片的物理属性体积小巧且功耗低,使其成为无人机应用的理想平台。该设计完全由硬件实现,由EA模块,人口存储资源和路径规划过程所必需的三维地形信息组成,这些条件受制于通过无人机,环境和任务配置文件单独考虑的约束。该架构已成功为目标Xilinx Virtex-4 FPGA平台进行了综合,具有32%的逻辑片利用率。从小型无人机直升机的案例研究中获得的结果来自具有来自LIDAR(光检测和测距)数据的环境,这证明了所提出的基于FPGA的路径规划器的有效性,并证明了以高于自动驾驶仪系统典型10 Hz更新频率的速率收敛。

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