Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence

摘要

For the requirements of different bus signals from high speed PCB with DDR3 components　based on fly-by topology structure, coping strategies have been proposed respectively. For the address　or command bus, a leveling-free strategy has been proposed. It shows that the phase difference can be　nearly zero through reasonable constraints on PCB design. The strategy was applied to the clock bus　and achieved good performance, combining with the rules of signal integrity. For the data bus, the　timing sequence on source synchronous has been analyzed and the time margin was calculated. The　reasonability of the design was verified through the simulation result with Cadence.