The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from ``QCD On a Chip''.
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机译：描述了针对格点QCD计算进行了优化的新型计算机的体系结构。单个节点基于单个集成电路，该集成电路包含PowerPC 32位整数处理器和1 Gflops 64位IEEE浮点单元，4 MB内存，8 Gbit / sec最近邻居通信以及其他控制和诊断电路。机器的名称QCDOC源自``QCD On a Chip''。
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