Soft errors are an ubiquitous, ever-increasing problem that will compromise future computing integrity at every echelon. Many architectures provide protection from these transient events for large arrays, such as register ?les and caches, but often, little is done to protect common latches from corruption, such as those used in con?guration and in the pipeline. It is important that we identify the most vulnerable processor components at the latch level, so as to mitigate soft errors before they manifest in architectural state. This research evaluates the vulnerability of latches within an IBM PowerPC-based processor core. We simulate a VHDL model of the processor and use an RTX error injection methodology to inject bit-?ips into the latch output nets at runtime. We then perform an analysis of the system?s behavior while executing various TST applications, paying particular attention to the ?oating point unit, and propose solutions to increase processor robustness.
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