A package efficient PC based AHPL to EDIF translator

摘要

Computed-Aided Design tools have assisted the digital designer at various levels of the design process. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described at the register transfer level. AHPL circuit descriptions can be translated into logic gate networks using the HPCOM hardware compiler. The Electronic Design Interchange Format (EDIF) is a data exchange standard used to exchange data between CAD tools. By providing a translator to convert the logic gate networks from HPCOM into EDIF Netlist format, designs described in AHPL can be ported to other CAD tools. This thesis documents the development and implementation of a EDIF Netlist translator for the HPCOM generated logic network. The translator is designed to use every gate in a package and includes an option that converts logic gates to their NAND equivalents. Netlist outputs from the translator are simulated with the OrCAD Verification and Simulation Tools. These simulations are then compared with simulations from HPSIM to make sure the netlist output from the translator is indeed a gate level representation of the design as described by AHPL.