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AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS

机译：AHPL（一种硬件编程语言）描述的同步顺序电路的测试序列生成的启发式搜索方法

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Belt John Edward 1933-;
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年度 1973
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正文语种 en_US
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1. Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits [J] . Pomeranz I., Reddy S.M. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2006,第6期

机译：透明DFT：针对同步时序电路的可测试性和测试生成方法的设计
2. On the role of hardware reset in synchronous sequential circuit test generation [J] . Pomeranz I., Reddy S.M. IEEE Transactions on Computers . 1994,第9期

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3. A hierarchical test generation approach using program slicing techniques on hardware description languages [J] . Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2003,第2期

机译：在硬件描述语言上使用程序切片技术的分层测试生成方法
4. Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences [C] . Irith Pomeranz, Sudhakar M. Reddy, PIrith Pomeranz, ACM/IEEE conference on Design automation . 1999

机译：基于测试子序列的加载和扩展，用于同步时序电路的内置测试序列生成
5. AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS, [D] . BELT, JOHN EDWARD. 1973

机译：一种针对AHPL（硬件编程语言）描述的同步顺序电路的测试序列生成的启发式搜索方法，
6. A new numerical approach to solve Thomas–Fermi model of an atom using bio-inspired heuristics integrated with sequential quadratic programming [O] . Muhammad Asif Zahoor Raja, Aneela Zameer, Aziz Ullah Khan, -1

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7. Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences + [O] . 2008

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8. Automatic Test Pattern Generation for Synchronous Sequential Circuits [R] . Konijnenburg, M. H. 1998

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AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS

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