Performance evaluation of microcomputer execution of AHPL combinational logic units

摘要

Design automation systems use Computer Hardware Description Languages as the input languages to test and verify the design of digital systems. AHPL is a popular hardware description language used to describe digital systems. This language is supported by a function-level simulator (HPSIM2). This simulator was upgraded (HPSIM2_CL) to support the use of unit description called Combinational Logic Units or CLUNITs. This thesis presents the transition of HPSIM2_CL from the VAX to the Macintosh microcomputer environment. The modifications made to the simulator are explained, and examples to test and analyze execution performance are also presented.