Two circuit model extractors for complex multilayer microelectronic packages based on the Partial Element Equivalent Circuit (PEEC) technique, namely University of Arizona Effective Package Inductance Calculator (UAEPIC) and University of Arizona Effective Package Inductance and Capacitance Calculator (UAEPIC²), have been developed. The first one, UAEPIC, is based on the magneto-quasistatic assumption where the displacement current effect on the derivation of the electromagnetic field integral equation is neglected and thus the dominant inductive effects are modeled in order to extract the RL equivalent model. The second one, UAEPIC², uses a more rigorous electromagnetic model that accounts for displacement (yet nonretarded) electromagnetic effects to extract the RLC equivalent model of the given microelectronic package. The development of electrical models of packages of high complexity requires the numerical solution of linear systems of several thousands of equations. This makes the development of a broadband equivalent circuit to include skin effect computationally expensive. To circumvent this difficulty, two model order reduction techniques have been utilized. The method of Asymptotic Waveform Evaluation (AWE) has been incorporated in UAEPIC, and the Passive Reduced-order Interconnect Macromodeling Algorithm (PRIMA) has been applied to UAEPIC². Applications of AWE and PRIMA provide orders of magnitude reduction in computation labor and lead to a direct multiport Y-matrix representation in terms of the poles and residues. In this form, and using a special algorithm, the multiport, frequency-dependent equivalent circuit of the package can be incorporated efficiently in a SPICE-like circuit simulator. This simulation capability facilitates rapid and accurate simulations for the analysis of noise generation and signal degradation such as delay, cross-talk, power and ground bounces, and Simultaneous Switching Noise (SSN) in the package.
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