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Design trade-off study for delta-doped Si/SiGe heterostructure MOSFET's: The potential nano-MOSFET's

机译:δ掺杂Si / SiGe异质结构MOSFET的设计折衷研究:潜在的纳米MOSFET

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摘要

A design trade-off study for n-channel δ-doped Si/SiGe heterojunction MOSFET's has been performed using a combination of numerical simulation and analysis. The design parameters unique to the δ-doped Si/SiGe heterostructure MOSFET's have been studied in terms of their effects on short-channel immunity, off-state leakage and on-state current. Our study shows that cap and channel layer must always be made as thin as possible to reduce the separation of the mobile charge centroid from the surface, in which case better short-channel immunity, better leakage and driving ability will result. On the other hand, the setback layer thickness, potential well depth and δ-doping dose are found to be trade-off parameters. Design windows that based on the trade-off parameters were constructed to obtained optimal designs for 0.2. μm channel length and 1.5 V supply voltage, and 0.1 μm channel length and 1 V supply voltage δ-doped Si/SiGe heterojunction MOSFET's. When compared to similarly configured conventional bulk MOSFET's, the 0.2 μm-1.5V design has approximately the same characteristics while the 0.1 μm-1V design has a 25% advantage in short-channel immunity. The δ-doped Si/SiGe heterojunction MOSFET is then redesigned by removing the cap layer, which results in a smaller effective oxide thickness but lower low-field mobility. The new structure is found to produce a 0.1μm-1V design that has improvement of 22% in on-state current, 54% in off-state leakage and 17% in short-channel immunity over the structure with the cap layer. We further are successful in producing a 70nm-1.2V design with excellent characteristics that cannot be reached by conventional MOSFET's. We conclude that the δ-doped Si/SiGe heterojunction MOSFET's without a cap layer have a high potential as the future high-performance transistors that can deliver high speed, high density and low power applications.
机译:结合数值模拟和分析,对n沟道δ掺杂Si / SiGe异质结MOSFET进行了设计折衷研究。已经研究了δ掺杂Si / SiGe异质结构MOSFET的独特设计参数,这些参数对短沟道抗扰度,关态泄漏和导通电流的影响。我们的研究表明,必须始终将帽盖和沟道层制作得尽可能薄,以减少移动电荷质心与表面的分离,在这种情况下,将获得更好的短沟道抗扰性,更好的泄漏和驱动能力。另一方面,发现挫折层厚度,势阱深度和δ掺杂剂量是权衡参数。构建基于折衷参数的设计窗口,以获得0.2的最佳设计。 μ沟道长度和1.5 V电源电压,以及0.1μm沟道长度和1 V电源电压δ掺杂的Si / SiGe异质结MOSFET。与配置类似的常规体MOSFET相比,0.2μm-1.5V设计具有大约相同的特性,而0.1μm-1V设计在短沟道抗扰度方面却具有25%的优势。然后,通过去除覆盖层来重新设计δ掺杂的Si / SiGe异质结MOSFET,这将导致更小的有效氧化物厚度,但更低的低场迁移率。发现这种新结构可产生0.1μm-1V的设计,与带有覆盖层的结构相比,该结构的导通电流提高了22%,关断态泄漏提高了54%,短沟道抗扰度提高了17%。我们进一步成功地生产出具有传统MOSFET无法达到的优异特性的70nm-1.2V设计。我们得出的结论是,不带盖层的δ掺杂Si / SiGe异质结MOSFET具有很高的潜力,因为它是可以提供高速,高密度和低功耗应用的未来高性能晶体管。

著录项

  • 作者

    Ip Brian Kau 1962-;

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  • 年度 1997
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  • 正文语种 en_US
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